1. Field of the Invention
The present invention relates to a redundancy IO (input/output) fuse circuit of a semiconductor device, and specifically, to a redundancy IO fuse circuit for overcoming signal delays arising from IO fuses employed in redundancy circuitry in a semiconductor device.
2. Discussion of Related Art
In a semiconductor device, it has been general to employ fuses in order to control IO (input/output) information to be repaired in a redundancy block. As a normal bit configuration of a semiconductor chip is ×8 or ×16, one repair line needs to be associated with four fuse boxes each of which includes a couple of fuses for setting high and low states.
FIG. 1A illustrates a conventional redundancy IO fuse circuit.
FIG. 1B is a circuit diagram of a region ‘A’ where a predetermined fuse is blown away in FIG. 1A.
Referring to FIGS. 1A and 1B, the conventional redundancy IO fuse circuit includes first through fourth fuse boxes FB1˜FB4 for outputting a predetermined logic signal in accordance with states of an external repair signal REP and fuse cutoff, and first through fourth NMOS transistors N1˜N4, connected between an external IO bus IOBUS and the first through fourth fuse boxes FB1˜FB4, for transferring an IO information signal to the IO bus IOBUS in accordance with the external repair signal REP.
The first fuse box FB1 is constructed of a first fuse F1 connected between an input terminal of the external repair signal REP and a drain node of the first NMOS transistor N1, and a second fuse connected between a ground voltage Vss and the drain node of the first NMOS transistor. The second through fourth fuse boxes FB2˜FB4 have the same structure with the first fuse box FB1, so will be omitted hereinafter.
An operation of the conventional IO fuse circuit shown in FIG. 1A is as follows. First, a defect on a chipset is cured by means of a predetermined test procedure. While this, an alternative one of the first and second fuses F1 and F2 in the first through fourth fuse boxes FB1˜FB4 is cut off (or blown out). For example, if IO<9> is to be repaired, the second fuses F2 each of the first and fourth fuse boxes FB1 and FB4 and the first fuses F1 each of the second and third fuse boxes FB2 and FB3 are cut off to set an output of IO bus IOBUS<0:3> on ‘1001’.
Therefore, when the repair signal REP becomes logically high, the first through fourth NMOS transistors N1˜N4 are turned on to output a logical-high signal of the repair signal REP or a logical-low signal of the ground voltage in accordance with fusing states from the first through fourth fuse boxes FB1˜FB4. The output signal from the first through fourth fuse boxes FB1˜FB4 is transferred to the IO bus IOBUS<0:3> through the first through fourth NMOS transistors N1˜N4 that is being turned on.
However, as illustrated in FIG. 1B, when a power supply voltage Vcc is applied to the first NMOS transistor N1 by the condition that the second fuse F2 is cut off and the external repair signal REP is logically high, there is a problem as follows.
First, it occurs a voltage drop by a threshold voltage of the NMOS transistor. Such a voltage drop causes the degradation of noise margins at an inverter connected to the IO bus, which is very disadvantageous to a low voltage chip operable under 1.8V of power supply voltage. Furthermore, the threshold voltage becomes higher due to a back bias effect of the NMOS transistor, making the noise margin of the inverter be degraded worse.
In addition, increasing a bias level of the IO bus causes a current decrease therein by the operational property of the NMOS transistor turns to a saturation mode into a linear mode, which means it takes a longer time for charging nodes of the IO bus and thereby consumes time delays.
Practically, a simulation result under the condition with Vcc=1.65V, slow skew, and 90° C. of temperature results in a transition time of 10 ns for changing the IO bus signal from low to high. And, it is difficult to obtain further improvement beyond about 1 ns although the NMOS transistor is enlarged in size. This time delay is regarded to as a very large value against an entire read/write time specification, acting as a serious factor degrading the performance of chip.